・ High speed D-Type Flip-Flip for data retiming with full rate clock.
・ 40GHz analog input bandwidth for bpth clock (CLK) and data (DATA).
・ 4ps set-up/hold time capability.
・ 84% clock phase margin for retiming of data input eye.
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■特徴/Key Features
Fully differential input and output buffers.
CML output interface with 500mW single-ended swing.
Single −4.0V power supply.
Industrial temperature range.
Power consumption: 500mW.
Standard MLF/QFN 24-pin package.