・ 1:16 Deserializer with clock and data recovery based on synchro signals extracted form the incoming data with a proprietary multi-level (ML) encoding.
・ Operates wit differential ML signals provided by ASNT01_12 MUX CMU.
・ On-chip PLL with two selectable VCOs centered at 12.5GHz and 8GHz.
・ High-speed Input Data Buffer with on-chip 100 Ohm differential termination.
・ Full-rate CML Input Clock Buffer with on-chip 50 Ohm signal-ended (SE) termination to the positive supply rail ("vcc")
・ LVDS Output Data Buffers with a proprietary low-power architechture.
・ Clock-divided-by-16 LVDS Output Buffer with 90°-step phase selection.
・ Digital Comparator for data comparison to an externally programmable threshold.
・ Selectable output FIFO for optical data realignment to an external master clock.
・ Single +3.3V power supply.
・ Industrial temperature range.
・ Low power consumption of 600mW at 12.5Gbps
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■特徴/Key Features
ASNT2012 is a high-speed 1:16 deserializer with clock and data recovery (CDR) based on synchro signals (SS) extracted from the incoming data with a proprietary multi-level (ML) encoding and rates up to 12.5Gbps. The primary application of ASNT2012 is to provide a high-speed inoput data channel for point-to-point data transmission over a controlled impedance media of 50 Ohm in combiantion with the ASNT01_12 MUX CMU. The transmission media can be a printed circuit board or copper coaxial cables. The functional distance of the data transfer is dependent upon the attenuation characteristics of the transportation media and the degreee of noise couplig to the signalimng environment.