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● High Speed Logic Family
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● High Speed Logic Family
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● High Speed Logic Family
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- Selectable number of channels from 0 to 10
- Single-ended 3.3V CMOS inputs
- LVDS outputs compliant with standards IEEE1596.3-1996 and ANSI/TIA/EIA-644-1995
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- High speed D-Type Flip-Flip for data retiming with full rate clock
- 40GHz analog input bandwidth for both clock and data
- 4ps set-up/hold time capability
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- High-speed clock amplifier and splitter for clock distribution
- 40GHz analog input bandwidth
- One input clock signal and three amplified output clock signal
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